AFSK modulation experiments - Part 2

AFSK modulation experiments - Part 2

Prelude

The experiments below were an initial attempt at modulation.  After posting this blog, I discovered I made an error.  the VC pin should take values between 0 .. 3v3.  I was attempting to modulate with an AC voltage, which was broken in several different ways.  Live and learn.

The erroneous post follows, for posterity.  However, corrections will be evident in blog posts made after this one.

Read below at your own peril.  I made lots of mistakes!!!

Test code

So, I'm using the Etherkit Library to generate my signals.  I used a little test code this evening to configure the VCXO and generate a signal at 144.330.  I then attached my signal generator to the VC pin and adjusted the frequency and amplitude to see if I could modulate my signal.  It worked!

The code is mostly just the example code available on his site.

// ASTXR-12-26.000MHz-512545 TCXO is 26 MHZ.  We use 0PF, since it's a TCXO and not a crystal.

MySi5351.init(SI5351_CRYSTAL_LOAD_0PF, 26000000UL, 0UL);

// power down the unused clocks

MySi5351.set_clock_pwr(SI5351_CLK1, DISABLE);

MySi5351.set_clock_pwr(SI5351_CLK2, DISABLE);

// Turn off transmit on unused clocks

XMITOFF(SI5351_CLK1);

XMITOFF(SI5351_CLK2);

MySi5351.set_clock_pwr(SI5351_CLK0, ENABLE);

XMITOFF(SI5351_CLK0);

MySi5351.drive_strength(SI5351_CLK0,SI5351_DRIVE_8MA); // Max power

MySi5351.set_vcxo(86598000000ULL, 40);

// Set CLK0 to be locked to VCXO

MySi5351.set_ms_source(SI5351_CLK0, SI5351_PLLB);

// Tune to 144.390 MHz center frequency

MySi5351.set_freq_manual(14433000000ULL, 86598000000ULL, SI5351_CLK0);

MySi5351.update_status();

MySi5351.output_enable(SI5351_CLK0, ENABLE);

Note, I have not yet fiddled with the PPM parameter as discussed in the previous blog.  I left it at "40" from the example.

Amplitude fiddling

I noticed that the amplitude of the signal generator output changed significantly when plugged into the VC pin.  I dialed the amplitude up and down until I reached a reasonable level, without distortion. I noted that under load, the P2P amplitude was about 1.16v.  When attached to the VC pin, the amplitude went down to about 0.6v p2p.

DAC fiddling

Knowing the amplitude, I was curious what output level the DAC would generate with the sine wave tables I was using for maximum amplitude.  Not surprisingly, it was about 3v p2p.  Not a shocker, since the Si5351 is operating at 3v3.  I needed to lower the amplitude of the DAC output to match what I was getting from the signal generator (1.16v).

The RC filter, tested in the Part 1 blog for this project, cleaned up the signal significantly, and also reduces the amplitude.  That's a start.

DC Blocking Cap

The signal generator makes an AC signal, swinging positive and negative.  The DAC makes a sine wave that is strictly positive.  I introduced a DC blocking cap into the circuit to convert it to AC, and clean it up a bit.

Test circuit

This circuit was sufficient to convert the DAC output to filtered AC.  The P2P voltage was about 1.5 volts, but it was sufficient for testing.  Sure 'nuff, it worked.  Putting the "AC Signal Out" from this filter into the VC pin on the Si5351b modulated the signal, and the tone created on the Nucleo DAC was readable on an FM receiver.

Progress!

Afterword

So, upon further examination, I discovered that I was in error.  The VC pin on the Si5351 requires 0 .. 3v3, all positive.  The experiments I was doing were generating an AC signal, but the modulation was faulty.  I'll have more on this in a future blog post.