Calculating the prescalar and counter values for WSPRI intend to use the TIM7 timer on the STM32L151CB microcontroller. TIM7 is fed from the APB1 clock source, which can be configured via the PLL in a number of ways (see below).
According to the WSPR spec: "Keying rate: 12000/8192 = 1.4648 baud (tones / second). If we flip that ratio, we will have seconds per tone: 8192 / 12000 = 0.682666 secs / tone.
The mathDoing some math, we have:
ticks_per_tone = AHB1_MHZ ticks/sec * (8,192 / 12,000) secs/tone
The 12,000 in the denominator will cause us some fits. Breaking down 12,000, it's 3*4*1000. The 3 is a problem. One way to cope is by putting a "3" in the numerator in AHB1.
AHB1 optionsI'm considering two speeds for AHB1 - 32MHZ, and 24 MHZ. The HSE is running at 16mhz. I can set the PLL multiplier to 4/2 for 32mhz, or to 3/2 for 24 MHZ.
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; // RCC_PLL_MUL3 for 24mhz
RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2;
At AHB1 = 32 MHZ
At 32 MHZ, the math looks like this.
ticks_per_tone = 32,000,000 * 8,192 / 12,000
ticks_per_tone = 32,000 * 8,192 / 12
ticks _per_tone = 8,000 * 8,192 / 3
ticks_per_tone = 21,845,333.33333At AHB1 = 24 MHZ
At 24 MHZ, the math looks like this.
ticks_per_tone = 24,000,000 * 8,192 / 12,000
ticks_per_tone = 2,000 * 8,192
ticks_per_tone = 216,000,000
Prescalar and CounterThe prescalar and counter for TIM7 are 16 bit values. Given that 8,192 is in the ticks_per_tone calculation, it becomes an attractive option for the prescalar.
|32,000,000||8,192||2,666.666 (round to 2,666)|
Switching AHB1 to 24mhz is a pretty minor concession. The ADCs would run a little slower, but I can think of little impact on functions I'd need for WSPR.
On the flip size, AHB1 at 32mhz means that each tone will be off by (.333 * 8192) = 2,730.66 ticks per tone. That's 2,730.66 / 32,000,000 = 0.0853 milliseconds per tone. Across the 162 tones of a WSPR message, we would end off by 13.82ms.
I'll be doing another blog post on establishing the "Top Of Second" for beginning the WSPR transmission. WSPR documentation shows that your clock should be within +/- 1 second. My objective is to be within 2ms. I think an added deviation of 13.82ms by the end is negligible in the grand scheme of things. I'm undecided at the moment, but I've tried both settings and the timing seems right, with some superficial stopwatch testing.